The First Hardware MSC Algorithm Implementation

Vit Fabera, Tomas Musil, Jakub Rada

Abstract


The paper describes the first attempt of hardware implementation of Multistream Compression (MSC) algorithm. The algorithm is transformed to series of finite state machines with data path using Register-Transfer methodology. Those state machines are then implemented in VHDL to selected FPGA platform. The algorithm utilizes a special tree data structure, called MSC tree. For storage purpose of the tree a Left Tree Representation is introduced. Due to parallelism, the algorithm uses multiple port access to SDRAM memory.


Keywords


Multistream compression;FPGA;MSC;Compression;Parallel compression;Left Tree Representation

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References


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DOI: http://dx.doi.org/10.14311/NNW.2017.029

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